View HA457CM_1056519.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HA457
Data Sheet August 1999 File Number 4231.2
95MHz, Low Power, AV = 2, 8 x 8 Video Crosspoint Switch
The HA457 is an 8 x 8 video crosspoint switch suitable for high performance video systems. Its high level of integration significantly reduces component count, board space, and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight video input signals to any, or all, matrix outputs. Each matrix output connects to an internal, high-speed (275V/s), gain of two buffer capable of driving 150 to 2.5V. The HA457 will directly drive a double terminated video cable with some degradation of differential gain and phase. Applications demanding the best composite video performance should drive the cable with a unity gain video buffer, such as the HFA1412 quad buffer (see Figure 7). This crosspoint's three-state output capability makes it feasible to parallel multiple HA457s and form larger switch matrices.
Features
* Pin Compatible, Cable Driving Upgrade for HA456 and MAX456 * Fully Buffered Inputs and Outputs (AV = +2) * Routes Any Input Channel to Any Output Channel * Switches Standard and High Resolution Video Signals * Serial or Parallel Digital Interface * Expandable for Larger Switch Matrices * Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 95MHz * High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . 275V/s * Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . -55dB
Applications
* Video Switching and Routing * Security and Video Editing Systems
Ordering Information
PART NUMBER HA457CN HA457CM TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 44 Ld MQFP 44 Ld PLCC PKG. NO. Q44.10x10 N44.65
Pinouts
HA457 (MQFP) TOP VIEW
D1/SER OUT D0/SER IN
HA457 (PLCC) TOP VIEW
A0 IN1 NC IN2 DGND NC IN3 DGND IN4 EDGE/LEVEL IN5
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 7 8 28 27 26
OUT2 VOUT3 AGND OUT4 NC AGND OUT5 AGND OUT6 V+
25 9 24 10 11 23 12 13 14 15 16 17 18 19 20 21 22
A0 IN1 NC IN2 DGND NC IN3 DGND IN4 EDGE/LEVEL IN5
IN0 A1 A2 D0/SER IN D1/SER OUT NC V+ OUT0 D2 OUT1 D3
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 54 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OUT0
OUT1
IN0
NC
A1
A2
D2
D3
V+
OUT2 VOUT3 AGND OUT4 NC AGND OUT5 AGND OUT6 V+
SER/PAR IN7
LATCH
1
OUT7
NC
CE
IN6
WR
CE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
SER/PAR IN7 VNC WR LATCH CE CE OUT7
V+
V-
V+ IN6
HA457 Functional Block Diagram
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7 OUTPUT BUFFERS (AV = 2)
+ EN0
OUT0
HA457 8x8 SWITCH MATRIX
+ EN7 EN0:7
OUT7
LATCH SLAVE REGISTER EDGE/LEVEL
SER/PAR MASTER REGISTER D0/SER IN
WR CE CE D1/SER OUT
A0
A1
A2
D2
D3
2
HA457 Pin Descriptions
PIN MQFP 3, 6, 17, 28, 39 40 PLCC 1, 9, 12, 23, 34 2 NAME NC D1/ SER OUT No connect. Not internally connected. Parallel Data Bit input D1 for parallel programming mode. Serial Data Output (MSB of shift register) for cascading multiple HA457s in serial programming mode. Simply connect Serial Data Out of one HA457 to Serial Data In of another HA457 to daisy chain multiple devices. Parallel Data Bit input D0 for parallel programming mode. Serial Data Input (input to shift register) for serial programming mode. Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode. Analog Video Input Lines. FUNCTION
41
3
D0/SER IN
42, 43, 1
4, 5, 7
A2, A1, A0
44, 2, 4, 7, 9, 11, 13, 15 5, 8 10
6, 8, 10, 13, 15, 17, 19, 21 11, 14 16
IN0-IN7
DGND EDGE/LEVEL
Digital Ground. Connect both DGND pins to AGND. A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin strapped high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL and LATCH low causes the channel switch to execute on the WR rising edge (not recommended for serial mode operation). Positive supply voltage. Connect all V+ pins together and decouple each pin to AGND (Figure 6). A user strapped input that defines whether the serial (SER/PAR=1) or parallel (SER/PAR=0) digital programming interface is being utilized. Negative supply voltage. Connect both V- pins together and decouple each pin to AGND (Figure 6). WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff D3:0=0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111), on the WR rising edge (see Table 1). Synchronous channel switch control input. If EDGE/LEVEL = 1, data is loaded from the Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0, data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111 executes a software "Latch" (see Table 1). Chip Enable. When CE = 0 and CE = 1, the WR line is enabled. Chip Enable. When CE = 0 and CE = 1, the WR line is enabled. Analog Video Outputs.
12, 23, 38
18, 29, 44
V+
14
20
SER/PAR
16, 32
22, 38
V-
18
24
WR
19
25
LATCH
20 21 22, 24, 26, 29, 31, 33, 35, 37 25, 27, 30 34 36
26 27 28, 30, 32, 35, 37, 39, 41, 43 31, 33, 36 40 42
CE CE OUT7-OUT0
AGND D3 D2
Analog Ground. Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming. Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.
3
HA457
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Positive Supply Voltage (V+) Referred to AGND . . . . . . . . . . . . . 6V Negative Supply Voltage (V-) Referred to AGND . . . . . . . . . . . . -6V DGND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND 1V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Digital Input Voltage . . . . . . . . . . . . . . (V+ + 0.3V) to (DGND - 0.3V) ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 1.6kV
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature, Soldering 10s . . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = 5V, AGND = DGND = 0V, RL = 400 (Note 2), Unless Otherwise Specified. (NOTE 3) TEST LEVEL A A A A TEMP (oC) 25 Full 25 Full 25 Full 25 Full Full Full 25 25 25 25 25 25 Full 25 Full Full 25 Full 25 25 25 25 Full Full
PARAMETER Voltage Gain
TEST CONDITIONS VIN = -0.75V to +0.75V, Worst Case Switch Configuration, RL = 150
MIN 1.93 2 -18 -20 2.45 1.5 45 -
TYP 1.97 0.04 68 71 47 47 2.5 1.6 0.15 22 4 3.2 2.5 -12 -15 4 8 20 2.6 0.25 2 3.5 2.9 53 -
MAX 2.10 0.1 80 83 65 67 12 5 6 11 1
UNITS V/V
Channel-to-Channel Gain Mismatch
V/V
Supply Current
All Outputs Enabled, RL = Open, VIN = 0V, Total for All V+ (3) or V- (2) Pins All Outputs Disabled, RL = Open, Total for All V+ (3) or V- (2) Pins
A A A A A
mA
Disabled Supply Current
mA
Input Voltage Range Analog Input Current Input Noise (RS = 75) Analog Input Resistance Analog Input Capacitance (Input Connected to One Output or All Outputs, Note 6) Input Offset Voltage VIN = 0V DC to 40MHz 10kHz DC PLCC Package MQFP Package VIN = 0V, Worst Case Switch Configuration
V A mVRMS nV/Hz M pF pF mV
A B B C B B A A A A B
Channel-to-Channel Input Offset Voltage Mismatch Input Offset Voltage Drift Output Voltage Swing VIN = 1.33V, RL = 150 Enabled, DC Output Disabled Output Capacitance (Output Disabled) Power Supply Rejection Ratio Digital Input Current (Note 5) PLCC Package MQFP Package DC, VS = 4.5V to 5.5V, VIN = 0V VIN = 0V or 5V
mV V/oC V V k pF pF dB A
A A
Output Resistance
B A B B A A
4
HA457
Electrical Specifications
VSUPPLY = 5V, AGND = DGND = 0V, RL = 400 (Note 2), Unless Otherwise Specified. (Continued) (NOTE 3) TEST LEVEL A A A SER OUT Logic Low Voltage SER OUT Logic High Voltage SER OUT Leakage Current Serial Mode, IOL = 1.6mA Serial Mode, IOH = -0.4mA Output Disabled, VOUT = 2.5V A A A A AC CHARACTERISTICS (Note 4) -3dB Bandwidth (Note 6) VOUT = 200mVP-P VOUT = 1VP-P VOUT = 2VP-P VOUT = 2VP-P, RL = 150 Slew Rate (Note 6) All Hostile Crosstalk (Note 6) VOUT = 4VP-P, RL = 150 10MHz, VIN = 1VP-P , RL = 150 10MHz, VIN = 1VP-P , RL = 1k All Hostile Off Isolation (Note 6) 10MHz, VIN = 1VP-P , RL = 150 10MHz, VIN = 1VP-P , RL = 1k Differential Phase NTSC or PAL, RL = 150 NTSC or PAL, RL = 1k NTSC or PAL, RL 10k Differential Gain NTSC or PAL, RL = 150 NTSC or PAL, RL = 1k NTSC or PAL, RL 10k TIMING CHARACTERISTICS (See Figure 8 for more information) Write Pulse Width High (tWH) Write Pulse Width Low (tWL) Chip-Enable Setup Time to Write (tCS) Chip-Enable Hold Time From Write (tCH) Data and Address Setup Time to Write (tDS) Data and Address Hold Time From Write (tDH) Latch Pulse Width (tL) Latch Delay From Write (tD) LATCH Edge to Output Disabled (tOFF) LATCH Edge to Output Enabled (tON) Output Break-Before-Make Delay (tON - tOFF) NOTES: 2. For the lowest crosstalk, and the best composite video performance, use RL 1k. 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. See AC Test Circuits (Figure 1 through Figure 4). 5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit. 6. See Typical Performance Curves for more information. Serial Mode Serial Mode Serial Mode Parallel Mode Serial Mode A A A A A A A A A B B B Full Full Full Full Full Full Full Full Full Full Full Full 20 20 5 5 20 20 25 40 40 30 185 155 ns ns ns ns ns ns ns ns ns ns ns ns B B B B B B B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 95 75 60 50 275 -55 -58 95 75 0.5 0.05 0.05 0.05 0.05 0.02 MHz MHz MHz MHz V/s dB dB dB dB DEG DEG DEG % % % TEMP (oC) Full 25 Full Full Full 25 Full
PARAMETER Digital Input Low Voltage Digital Input High Voltage
TEST CONDITIONS
MIN 2.0 2.2 3.0 -
TYP 0.2 1
MAX 0.8 0.4 5 10
UNITS V V V V V A A
5
HA457 AC Test Circuits
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VOUT IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT
VIN = 1VP-P, SWEEP FREQUENCY
VIN = 1VP-P, AT 10MHz
FIGURE 1. -3dB BANDWIDTH (NOTES 7-10)
FIGURE 2. ALL HOSTILE OFF ISOLATION (NOTES 10-12)
IN0 IN1 IN2 IN3 7 X 75 IN4 IN5 IN6 IN7
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
VOUT VOUT VOUT VOUT VOUT VOUT VOUT 75
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
VOUT
VIN = 1VP-P, AT 10MHz
VIN = 1VP-P, AT 10MHz
FIGURE 3. SINGLE CHANNEL CROSSTALK (NOTES 10, 13-16) NOTES: 7. Program the desired input to output combination (e.g., IN7 to OUT1). 8. Enable the selected output(s).
FIGURE 4. ALL HOSTILE CROSSTALK (NOTES 10, 15, 17-19)
9. Drive the selected input with VIN, and measure the -3dB frequency at the selected output (VOUT). 10. Load all outputs with the desired RL. 11. Disable all outputs. 12. Drive all inputs with VIN and measure VOUT at any output; Isolation (in dB) = -20log10 (VOUT/VIN). 13. Drive VIN on one input which connects to one output (e.g., IN7 to OUT7). 14. Terminate all other inputs to GND. 15. Enable all outputs. 16. Measure VOUT at any undriven output; Crosstalk (in dB) = 20log10 (VOUT/VIN). 17. Terminate one input to GND, and connect that input to a single output (e.g., IN0 to OUT0). 18. Drive the other seven inputs with VIN, and connect these active inputs to the remaining seven outputs. 19. Measure VOUT at the quiescent output; Crosstalk (in dB) = 20log10 (VOUT/VIN).
6
HA457
HA457 75 VIDEO OUT 75
VIDEO INPUTS
INPUT BUFFERS
WR LATCH
8X8 SWITCH MATRIX
AV = 2
OUTPUT SELECT
A2 A1 A0 D3 D2 D1/SER OUT D0/SER IN
INPUT SELECT AND COMMAND CODES OR SERIAL I/O
FIGURE 5. TYPICAL CABLE DRIVING APPLICATION
Application Information
HA457 Architecture
The HA457 video crosspoint switch consists of 64 switches in an 8 x 8 grid (Figure 5). Each input is fully buffered and presents a constant input capacitance whether the input connects to one output or all eight outputs. This yields consistent input termination impedances regardless of the switch configuration. The 8 matrix outputs are followed by 8 gain of 2, wideband, three-stateable buffers optimized for driving 1k loads. Double terminated video cables (RL = 150) may be driven if degraded differential phase is acceptable (see "Electrical Specification" Table). The output disable function is useful for multiplexing two or more HA457s to create a larger input matrix (e.g., two multiplexed HA457s yield a 16x8 crosspoint). The HA457 outputs can be disabled individually or collectively under software control. When disabled, an output enters a pseudo high-impedance state (ROUT = 2k). In multichip parallel applications, the disable function prevents inactive outputs from loading lines driven by other devices. Disabling an unused output also reduces power consumption. The HA457 outputs connect easily to two HFA1412 quad, unity gain buffers when 75 loads must be driven with excellent differential phase (see Figures 7 and 21). The bandwidth improves to 120MHz, while differential gain and differential phase improve to 0.03% and 0.09 degrees, respectively.
the desired switch state may be programmed before the outputs are enabled. In serial mode, all outputs are connected to GND each time they are enabled, so switch state programming must occur after the output is enabled.
Digital Interface
The desired switch state can be loaded using a 7-bit parallel interface mode or 32-bit serial interface mode (see Tables 1 through 3). All actions associated with the WR line occur on its rising edge. The same is true for the LATCH line if EDGE/LEVEL=1. Otherwise, the Slave Register updates asynchronously (while LATCH=0, if EDGE/LEVEL=0). WR is logically ANDed with CE and CE to allow active high or active low chip enable.
7-Bit Parallel Mode
In the parallel programming mode (SER/PAR = 0), the 7 control bits (A2:0 and D3:0) typically specify an output channel (A2:0) and the corresponding action to be taken (D3:0). Command codes are available to enable or disable all outputs, or individual outputs, as shown in Table 1. Each output has 4-bit Master and Slave Registers associated with it, that hold the output's currently selected input address (defined by D3:0). The input address - if applicable - is loaded into the Master Register on the rising edge of WR. If the HA457 is in level mode, and if LATCH=0 (asynchronous switching), then the input address flows through the transparent Slave Register, and the output immediately switches to the new input. For synchronous switching on the rising edge of LATCH, strap the HA457 for edge mode, program all the desired switch connections, and then drive an inverted pulse on the LATCH input. Note: Operations defined by commands 1011 - 1111 occur asynchronously on the WR rising edge, without regard for the state of LATCH or EDGE/LEVEL.
Power-On RESET
The HA457 has an internal power-on reset (POR) circuit that disables all outputs at power-up, and presets the switch matrix so that all outputs connect to IN0. In parallel mode,
7
HA457
32-Bit Serial Mode
In the serial programming mode, all master registers are loaded with data, making it unnecessary to specify an output address (A2:0). The input data format is D3-D0, starting with OUT0 and ending with OUT7 for 32 total bits (i.e., first bit shifted in is D3 for OUT0, and 32nd bit shifted in is D0 for OUT7). Only codes 0000 through 1010 are valid serial mode commands. Code 1010 disables an individual output, while code 1001 enables it. After data is shifted into the 32-bit Master Register, it transfers to the Slave Register on the rising edge of the LATCH line (Edge mode), or when LATCH = 0 (Level mode, see Figure 10). Figure 6 shows a typical application of the HA457 for driving 75 loads. This application shows the HA457 digital-switch control interface set up in the 7-bit parallel mode. The HA457 uses 7 data lines and 3 control lines (WR, CE and LATCH). The input/output information is presented to the chip at A2:0 and D3:0 by a parallel printer port. The data is stored in the master registers on the rising edge of WR. When the LATCH line goes high, the switch configuration loads into the slave registers, and all 8 outputs reconfigure at the same time. Each 7-bit word updates only one output at a time. If several outputs are to be updated, the data is individually loaded into the master registers. Then, a single LATCH pulse can reconfigure all channels simultaneously. An IBM compatible PC loads the programming data into the HA457 via its parallel port (LPT1) using a simple BASIC program.
TABLE 1. PARALLEL INTERFACE COMMANDS A2:0 Selects Output Being Programmed D3:0 0000 to 0111 1000 1011 1100 Address Inputs are Irrelevant for These Functions 1101 1110 1111 1001 or 1010 ACTION Connect the input defined by D3:0 to the output selected by A2:0. Doesn't enable a disabled output. Connect the output selected by A2:0 to GND. Doesn't enable a disabled output. Asynchronously disable the single output selected by A2:0, and leave the Master Register unchanged. Asynchronously enable the single output selected by A2:0, and leave the Master Register unchanged. Asynchronously disable all outputs, and leave the Master Register unchanged. Asynchronously enable all outputs, and leave the Master Register unchanged. Send a Software pulse to the Slave Register to load it from the Master Register, iff, the LATCH input=1. If the LATCH input=0, then this command is a NOP. The Master Register is unchanged by this command. Do not use these codes in the parallel programming mode. These codes are for serial programming only. TABLE 2. SERIAL INTERFACE COMMANDS D3:0 0000 to 0111 1000 1001 1010 1011 to 1111 ACTION Connect the output to the input channel defined by D3:0. Doesn't enable a disabled output. Connect the output to GND. Doesn't enable a disabled output. Enable the output and connect it to GND. The default power-up state is all outputs disabled, so use this code to enable outputs after power is applied, but before programming the switch configuration. Disable the output. The output is no longer associated with any input channel; the desired input must be redefined after reenabling the output. Do not use these codes in the serial programming mode. TABLE 3. DEFINITION OF DATA AND ADDRESS BIT FUNCTIONS SER/PAR H D3 X D2 X D1 Serial Data Output Parallel Data Input Parallel Data Input D0 Serial Data Input Parallel Data Input Parallel Data Input A2:0 X COMMENT 32-Bit Serial Mode
L L
H L
Parallel Data Input Parallel Data Input
Output Address Output Address
Parallel Mode; D2:0 define the command to be executed. Parallel Mode; D2:0 define the Input Channel
8
HA457
HA457 (MQFP PINOUT) 44 2 4 7 9 11 13 15 OUT0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 CE EDGE/LEVEL 19 1 2 3 4 5 6 7 8 14 16 18 NC 18 WR V+ 41 40 36 34 1 43 42 D0/SER IN AGND D1/SER OUT DGND D2 VD3 A0 A1 SER/PAR A2 CE 19 LATCH 37 75 35 33 31 29 26 24 22 21 10 75
VIDEO INPUTS
12, 23, 38 25, 27, 30 5, 8 16, 32
+5V
-5V
30 33 36
14 20 NOTES: ALL DECOUPLING CAPACITORS 0.1F CERAMIC (1 PER SUPPLY PIN) FOR LOWEST CROSSTALK CONNECT UNUSED PINS TO GND
FIGURE 6. TYPICAL CABLE DRIVING, PARALLEL MODE APPLICATION CIRCUIT
HFA1412 (AV = +1) HA457 (MQFP PINOUT) 44 2 4 7 9 11 13 15 OUT0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 CE EDGE/LEVEL 19 1 2 3 4 5 6 7 8 14 16 18 NC 18 WR V+ 41 40 36 34 1 43 42 D0/SER IN AGND D1/SER OUT DGND D2 VD3 A0 A1 SER/PAR A2 CE 19 LATCH 37 35 33 31 29 26 24 22 21 10 RS RS 3 IN 1 5 IN 2 10 IN 3 12 IN 4 V+ 4 OUT1 1 7 OUT2 8 OUT3 14 OUT4 -IN0:3 2, 6 9, 13 NC -5V V11 75 VOUT 75
VIDEO INPUTS
RS
12, 23, 38 25, 27, 30 5, 8 16, 32
+5V
-5V
30 33 36
14 20 NOTES: ALL DECOUPLING CAPACITORS 0.1F CERAMIC (1 PER SUPPLY PIN) FOR LOWEST CROSSTALK CONNECT UNUSED PINS TO GND USE RS TO TUNE THE OVERALL OUTPUT RESPONSE
FIGURE 7. TYPICAL HIGH PERFORMANCE (IMPROVED DG, DP) APPLICATION CIRCUIT (SEE FIGURE 21)
9
HA457 Waveforms
A2:0, D3:0 VALID DATA VALID DATA tDS tCS CE
tDH tCH
tWL WR tD LATCH (EDGE MODE) tL tWH
FIGURE 8. DIGITAL TIMING REQUIREMENTS
DATA (N)
DATA (N + 1)
DATA (N + 2)
WR LATCH
MASTER REGISTER CONTENTS
DATA (N)
DATA (N + 1)
DATA (N + 2)
SLAVE REGISTER CONTENTS (EDGE/LEVEL = 0) SLAVE REGISTER CONTENTS (EDGE/LEVEL = 1)
DATA (N)
DATA (N + 1)
DATA (N + 2)
DATA (N)
DATA (N + 1)
DATA (N + 2)
FIGURE 9. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)
NEW DATA FOR OUT0
NEW DATA FOR OUT1 TO OUT6
NEW DATA FOR OUT7
SER IN
D3
D2
D1
D0
D3
D2
D3
D2
D1
D0
WR
1ST WRITE
32ND WRITE
LATCH
t=0
SLAVE REGISTER CONTENTS (EDGE/LEVEL = 0) OLD DATA NEW DATA
SLAVE REGISTER CONTENTS (EDGE/LEVEL = 1)
OLD DATA
NEW DATA
FIGURE 10. SERIAL PROGRAMMING MODE OPERATION (SER/PAR = 1)
10
HA457 Typical Performance Curves
1.75 1.50 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TIME (20ns/DIV.) 1.25 1.0 0.75 0.50 0.25 0 -0.25
VSUPPLY = 5V, TA = 25oC, RL = 150, Unless Otherwise Specified
4.0 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 -4.0 TIME (20ns/DIV.)
FIGURE 11. SMALL SIGNAL PULSE RESPONSE
FIGURE 12. LARGE SIGNAL PULSE RESPONSE
GAIN (dB)
3 0 -3 -6 GAIN (dB) VOUT = 2VP-P PHASE (DEGREES) PHASE 0 45 VOUT = 2VP-P 90 135 VOUT = 1VP-P VOUT = 0.2VP-P 1 10 FREQUENCY (MHz) 100 200 1 10 FREQUENCY (MHz) 100 200 180 GAIN VOUT = 0.2VP-P VOUT = 1VP-P 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 VOUT = 0.2VP-P VOUT = 1VP-P
FIGURE 13. FREQUENCY RESPONSE
FIGURE 14. GAIN FLATNESS
3 GAIN (dB) 0 -3 -6 PHASE PHASE (DEGREES) 0 45 VOUT = 0.2VP-P 90 135 VOUT = 1VP-P RL = 400 1 VOUT = 2VP-P 10 FREQUENCY (MHz) 100 180 200 GAIN VOUT = 1VP-P VOUT = 2VP-P GAIN (dB) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 RL = 400 1 10 FREQUENCY (MHz) 100 200 VOUT = 0.2VP-P VOUT = 1VP-P VOUT = 0.2VP-P
FIGURE 15. FREQUENCY RESPONSE
FIGURE 16. GAIN FLATNESS
11
HA457 Typical Performance Curves
-10 VIN = 1VP-P -20 -30 OFF ISOLATION (dB) CROSSTALK (dB) -40 RL = 150 -50 RL = 1k -60 -70 -80 -90 -100 1 10 FREQUENCY (MHz) 100 200
VSUPPLY = 5V, TA = 25oC, RL = 150, Unless Otherwise Specified (Continued)
20 VIN = 1VP-P 30 40 50 60 70 RL = 150 80 90 100 110 1 10 FREQUENCY (MHz) 100 200 RL = 1k
FIGURE 17. ALL HOSTILE CROSSTALK
FIGURE 18. ALL HOSTILE OFF-ISOLATION
400 350 300 SLEW RATE (V/s) 250 200 150 100 MAGNITUDE (dB)
120 110 1 INPUT TO ALL OUTPUTS 100 90 1 INPUT TO 1 OUTPUT 80 70 60 PHASE 0 10 PHASE (DEGREES)
50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOUT (VP-P) 4.0 4.5 5.0 5.5
20 0.03 0.1 1 FREQUENCY (MHz) 10 30 100
FIGURE 19. SLEW RATE vs VOUT
FIGURE 20. INPUT IMPEDANCE vs FREQUENCY
RS = 0
GAIN (dB)
3 0 -3 -6 VOUT = 1VP-P
1
10 FREQUENCY (MHz)
100
200
FIGURE 21. FREQUENCY RESPONSE OF HA457-HFA1412 (AV = 1) COMBINATION (PER FIGURE 7)
12
HA457 Metric Plastic Quad Flatpack Packages (MQFP)
D D1 -D-
Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 A2 MIN 0.004 0.077 0.012 0.012 0.515 0.389 0.516 0.390 0.029 44 0.032 BSC MAX 0.096 0.010 0.083 0.018 0.016 0.524 0.399 0.523 0.398 0.040 MILLIMETERS MIN 0.10 1.95 0.30 0.30 13.08 9.88 13.10 9.90 0.73 44 0.80 BSC MAX 2.45 0.25 2.10 0.45 0.40 13.32 10.12 13.30 10.10 1.03 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. "N" is the number of terminal positions.
0.13/0.23 0.005/0.009
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.076 0.003 12o-16o 0.40 0.016 MIN 0o MIN 0o-7o A2 A1 0.20 M C A-B S 0.008 -CDS b b1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING
E1 L N e
-H-
L
12o-16o
13
HA457 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP
N44.65 (JEDEC MS-018AC ISSUE A)
0.004 (0.10) C
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.685 0.650 0.291 0.685 0.650 0.291 44 MAX 0.180 0.120 0.695 0.656 0.319 0.695 0.656 0.319 MILLIMETERS MIN 4.20 2.29 17.40 16.51 7.40 17.40 16.51 7.40 44 MAX 4.57 3.04 17.65 16.66 8.10 17.65 16.66 8.10 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L E1 E D2/E2 VIEW "A"
D D1 D2 E E1 E2 N
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN
0.025 (0.64) MIN VIEW "A" TYP.
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
14

▲Up To Search▲

Price & Availability of HA457CM

	To Download HA457CM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .